Strained channel field effect transistors may exhibit performance characteristics differing from, and in some circumstances superior to, those of unstrained channel field effect transistors. Related art methods of fabricating strained channel field effect transistors may have various drawbacks. For example, the use of source drain (SD) stressors may become less efficient with scaling due to smaller SD volume. Also, SD stressors may be poorly suited for achieving tensile strained channels in n-type metal oxide semiconductor (nMOS) devices. Flows with built in stressed layers as starting material and flows using underlayer stressors may face difficulties in maintaining the stress through the fabrication flow, losing, for example, most of the initial stress. In particular, stress may be lost during deep SD recess and/or fin cut, due to elastic relaxation. This strain loss may not be fully recovered during SD epitaxial regrowth. With significant effort in the epitaxial SD regrowth module, some strain may be partially recovered, but in some cases practically no strain recovery occurs at this module. If the deep SD recess is eliminated and epitaxial growth is added on top of the fin structure on the SD, without previously performing a SD recess, poor doping profiles may result.
Thus, there is a need for a method for fabricating strained channel field effect transistors that addresses these challenges.